Low Power VLSI Design for Signal Processing Systems

  As VLSI technology continues to advance, more and more complex algorithms are being integrated onto a single chip in order to improve system performance. On the other hand, the proliferation of portable computing devices, the need to reduce packaging cost, 
and the desire to extend operation of VLSI systems, has made low power dissipation a critical design concern.

  In this talk, power consumption and basic low-power design strategies for digital integrated circuits will be briefly introduced. Then, an introduction to VLSI Signal Processing and an overview of my research in the area will be presented. A few interesting projects will be shortly discussed in particular. Thereafter, two specific topics will be discussed in detail: 1) Low Power High Throughput Turbo Decoder Design, 2) Low Complexity High Speed Low Density Parity Check (LDPC) Codes Codec Design.

  Error correction codes have been extensively used in digital communication systems. Typical applications include cellular wireless, wireless LAN, wire-line communication systems, disk drive, deep space communications, digital video broadcasting and Ethenet.  Turbo codes and Low Density Parity Check (LDPC) codes are two most attractive near-Shannon limit error correction codes. They can provide very reliable (e.g., bit-error-rate < ) digital transmission with practically lowest transmission power. Turbo codes are a class of parallel concatenated convolutional coding schemes. LDPC codes are a class of block codes characterized with very sparse parity check matrix.  Both codes use iterative decoding in order to provide outstanding performance with moderate complexity. However, iterative decoding directly leads to low throughput and high latency. In this talk, a few innovative ideas will be presented and discussed. These include efficient high-speed architectures for MAP decoders, novel VLSI architectures for area-efficient parallel turbo decoding architectures, modified Sum-Product algorithm and VLSI architectures as well as enhanced partially parallel decoding architectures for LDPC codes.  It will be shown that the proposed turbo-decoder architecture can achieve 3 to 4 times speedup over conventional designs through introducing about 25% extra hardware. We will also show that a very high speed LDPC decoder implemented with Xilinx FPGA can process more than twice higher data rate than any existing (FPGA) design with comparable code sizes.

  ABOUT THE SPEAKER: Dr. Zhongfeng Wang received both the B.Sc.(1988) and the M.S.(1990) degrees from the Department of Automation at the Tsinghua University, Beijing, CHINA. He earned his Ph.D. in 2000 from the Department of Electrical and Computer Engineering, University of Minnesota,Minneapolis, USA. He was the recipient of the Best Student Paper Award at the 1999 IEEE Workshop on Signal Processing Systems (SiPS’99). Upon finishing his graduate study, he worked for Morphics Technology (now part of Infineon Technology) and then for National Semiconductor Corp. Since September 2003, he has been an Assistant Professor with the School of EECS at the Oregon StateUniversity. He has published numerous technical papers and filed four U.S. Patent applications based on his research. His current research interests are in the area of efficient design and (VLSI) implementation of error-correction codes, digital communications, and cryptographic systems. Dr. Wang is a member of Sigma Xi and senior member of the IEEE. He is currently serving as an Associate Editor for the IEEE Transactions on Circuits and Systems: I.