期刊论文 [1] 胡庆生, 许多等. 40Gbps甚短距离并行光传输技术与实验系统[J].电子学报, 2011, Vol.39, no.5:1174-1177. [2] Zhang Xiaowei, Hu Qingsheng. A 6.25 Gbps CMOS 10B/8B decoder with pipelined architecture [J]. Journal of Semiconductors, Vol. 32, no. 4, April 2011. [3] Hu Qingsheng, Zhao Hua-An. Design and implementation of high-speed input-queued switches based on a fair scheduling algorithm[J]. IEICE Transactions on Electronics, Vol. E93-C, no. 3, p 279-287, 2010. [4] 许多,胡庆生等. 40Gbps 甚短距离并行光传输系统接收电路的设计与实现[J]. 高技术通讯, Vol. 20, no.1, p 82-88, January 2010. [5] Zhang Liang, Wang Zhigong, Hu Qingsheng. 基于移位多项式基优化并行RS伴随式计算电路的方法[J]. 高技术通讯, v 20, no.12, p 1274-1280, December 2010. [6] 张亮, 王志功, 胡庆生. 并行BCH伴随式计算电路的优化[J]. 信号处理, Vol. 26, no. 3, p 35-8, 25, March 2010 [7] 方亮亮,胡庆生. 基于Hermes NoC的片上网络容错方法研究[J]. 电子器件, 2010, Vol. 33, No. 1. [8] Zhang, Liang, Wang, Zhigong; Hu, Qingsheng. Modeling for Ethernet passive optical network receiver[J]. Journal of SoutheastUniversity(English Edition), Vol. 25, no.4, p 439-444, December 2009. [9] 徐捷, 胡庆生等. 40Gbit/s甚短距离光传输系统发送模块的设计与实现[J]. 东南大学学报(自然科学版), Vol. 39, no.4, p 656-661, July 2009. [10] 白玉洁, 胡庆生. 电力线通信中降低峰均比的有效方法[J]. 电子器件, 2009, Vol. 32, no. 1: 114-117. [11] Hu Qingsheng,Zhong Jianfeng; He Xiaohu.0.18mCMOS programmable frequency divider design for DVB-T[J]. Journal ofSoutheastUniversity(English Edition), Vol. 24, no. 2, p 159-162, June 2008 [12] 胡庆生,孙远等. 输入队列交换的公平可扩展调度算法[J]. 电路与系统学报, 2008, Vol. 13, no. 6: 40-46. [13] 王辉, 汪晓岩,胡庆生. 基于电力线信道的OFDM同步算法的仿真[J]. 电力系统通信, 2008, Vol.29, no.8. [14] He Xiaohu, Hu Qingsheng. Design of0.18mm CMOS programmable frequency divider based on standard cells [J]. Journal ofSoutheastUniversity(English Edition), Vol. 23, no. 1, p 31-34, March 2007. [15] Hu qingsheng, Sun Yuan. An efficient scheduling algorithm for input-queued switches [J]. Journal of Electronics, 2007, Vol.24, no.2:245-250. [16] Hu Qingsheng, Wang Zhigong. Area optimization of parallel Chien search architecture for Reed-Solomon (255, 239) decoder [J]. Journal ofSoutheastUniversity(English Edition), Vol. 22, no. 1, p 5-10, March 2006. [17] 张军,王志功,胡庆生等. 并行钱氏搜索电路优化及高速RS译码器设计[J]. 固体电子学研究与进展, 2005, Vol.25, no.3 [18] 胡庆生, 王志功等. 2.5Gb/s Reed-Solomon 译码器的VLSI优化实现[J]. 电路与系统学报, 2005, Vol.10. no.2.
会议论文 [1] Yu Zhen and Hu Qing-sheng. A Comma Detection and Word Alignment Circuit for High-speed SerDes[C]. To appear in WiCom 2011. [2] Feng Zhuangjin and Hu Qingsheng. A 6.25Gb/s Decision Feedback Equalizer in 0.18mm CMOS Technology for High-speed SerDes. To appear in WiCom 2011. [3] Song Yu-yun, Hu Qing-sheng. A 0.18mm Pipelined 8B10B Encoder for a High-speed SerDes[C]. International Conference on Communication Technology, ICCT 2010. [4] Hu Qingsheng, Sun Chengkun, Zhao Hua-An. 10Gb/s RS-BCH concatenated codec with parallel strategies for fiber communications[C]. 2010 International Conference on Communications, Circuits and Systems, ICCCAS 2010 - Proceedings, p 303-307, 2010. [5] Hu Qingsheng, Liu Chen, Zhao Hua-An. A practical scheduling architecture and its implementation for input-queued switches[C]. 2009 International Conference on Communications, Circuits and Systems, ICCCAS 2009, p 177-181, 2009. [6] Zhang Liang, Wang Zhigong, Hu Qingsheng. Modeling for Ethernet Passive Optical Network link[C]. 2009 WRI International Conference on Communications and Mobile Computing, CMC 2009, v 2, p 471-476. [7] Zhang Liang, Wang Zhigong, Hu Qingsheng. High speed concatenated code codec for optical communication systems[C]. Symposium on Photonics and Optoelectronics, SOPO 2009. [8] Xu Jie, Hu Qingsheng. Implementation of 40Gb/s converter for very short reach optical transmission system[C]. Proceedings of SPIE, Optical Transmission, Switching, and Subsystems VI, vol 7136, 2008. [9] Hui Wang, Qingsheng Hu, Xiaoyan Wang. A New OFDM Synchronization Scheme for PLC[C]. Proceedings - 2008 International Seminar on Future Information Technology and Management Engineering, FITME 2008, p 604-607. [10] Sun Yuan, Hu Qingsheng, Zhong Jianfeng. Design of fair scalable scheduling architecture for input-queued switches[C]. 2007 IEEE Workshop on High Performance Switching and Routing, HPSR, p 106-110 [11] Hu Qingsheng, Liu Chen, Zhao Hua-An. A high-speed fair scalable scheduling architecture[C]. 2007 International Symposium on Intelligent Signal Processing and Communications Systems, ISPACS 2007, p 60-63 [12] Sun Yuan and Hu Qingsheng. A self-adaptive threshold based scheduling algorithm for input-queued switches[C]. 2006 Workshop on High Performance Switching and Routing, HPSR 2006, p 393-396. [13] Hu Qingsheng. Low Complexity Parallel chien Search Architecture for RS Decoder[C]. Proc. of the ISCAS’05,Japan, 2005. [14] Zhang Jun, Wang Zhi-gong and Hu Qing-sheng. Optimized design for high-speed parallel BCH Encoder. 2005 IEEE International Workshop on VLSI Design and Video Technology, 2005. |