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10.17  Summary

Table 10.27 shows the essential elements of the VHDL language. Table 10.28 shows the most important BNF definitions and their locations in this chapter. The key points covered in this chapter are as follows:

• The use of an entity and an architecture
• The use of a configuration to bind entities and their architectures
• The compile, elaboration, initialization, and simulation steps
• Types, subtypes, and their use in expressions
• The logic systems based on BIT and Std_Logic_1164 types
• The use of the IEEE synthesis packages for BIT arithmetic
• Ports and port modes
• Initial values and the difference between simulation and hardware
• The difference between a signal and a variable
• The different assignment statements and the timing of updates
• The process and wait statements

VHDL is a "wordy" language. The examples in this chapter are complete rather than code fragments. To write VHDL "nicely," with indentation and nesting of constructs, requires a large amount of space. Some of the VHDL code examples in this chapter are deliberately dense (with reduced indentation and nesting), but the bold keywords help you to see the code structure. Most of the time, of course, we do not have the luxury of bold fonts (or color) to highlight code. In this case, you should add additional space, indentation, nesting, and comments.

TABLE 10.27    VHDL summary.
VHDL feature	Example	Book	93LRM
Comments	-- this is a comment	10.3	13.8
Literals (fixed-value items)	12   1.0E6   '1'   "110"   'Z' 2#1111_1111#    "Hello world" STRING'("110")	10.4	13.4
Identifiers (case-insensitive, start with letter)	a_good_name   Same   same 2_Bad   bad_   _bad   very__bad	10.4	13.3
Several basic units of code	entity    architecture    configuration	10.5	1.1-1.3
Connections made through ports	port ( signal in i : BIT; out o : BIT);	10.7	4.3
Default expression	port (i : BIT := '1'); -- i='1' if left open	10.7	4.3
No built-in logic-value system. BIT and BIT_VECTOR (STD).	type BIT is ('0', '1'); -- predefined signal myArray: BIT_VECTOR (7 downto 0);	10.8	14.2
Arrays	myArray(1 downto 0) <= ('0', '1');	10.8	3.2.1
Two basic types of logic signals	a signal corresponds to a real wire a variable is a memory location in RAM	10.9	4.3.1.2 4.3.1.3
Types and explicit initial/default value	signal ONE : BIT := '1' ;	10.9	4.3.2
Implicit initial/default value	BIT'LEFT = '0'	10.9	4.3.2
Predefined attributes	clk'EVENT, clk'STABLE	10.9.4	14.1
Sequential statements inside processes model things that happen one after another and repeat	process begin wait until alarm = ring; eat; work; sleep; end process;	10.10	8
Timing with wait statement	wait for 1 ns; -- not wait 1 ns wait on light until light = green;	10.10.1	8.1
Update to signals occurs at the end of a simulation cycle	signal <= 1; -- delta time delay signal <= variable1 after 2 ns;	10.10.3	8.3
Update to variables is immediate	variable := 1; -- immediate update	10.10.3	8.4
Processes and concurrent statements model things that happen at the same time	process begin rain ; end process ; process begin sing ; end process ; process begin dance; end process ;	10.13	9.2
IEEE Std_Logic_1164 (defines logic operators on 1164 types)	STD_ULOGIC , STD_LOGIC , STD_ULOGIC_VECTOR , and STD_LOGIC_VECTOR type STD_ULOGIC is ('U','X','0','1','Z','W','L','H','-');	10.6	--
IEEE Numeric_Bit and Numeric_Std (defines arithmetic operators on BIT and 1164 types)	UNSIGNED and SIGNED X <= "10" * "01" -- OK with numeric pkgs.	10.12	--

TABLE 10.28    VHDL definitions.
Structure	Page	BNF		Structure	Page	BNF
alias declaration	418	10.21		next statement	429	10.32
architecture body	394	10.8		null statement	430	10.35
assertion statement	423	10.25		package declaration	398	10.11
attribute declaration	418	10.22		port interface declaration	406	10.13
block statement	438	10.37		port interface list	406	10.12
case statement	428	10.30		primary unit	393	10.5
component declaration	395	10.9		procedure call statement	427	10.28
component instantiation	444	10.42		process statement	440	10.38
concurrent statement	438	10.36		return statement	430	10.34
conditional signal assignment	442	10.40		secondary unit	393	10.6
configuration declaration	396	10.10		selected signal assignment	442	10.39
constant declaration	414	10.16		sequential statement	419	10.23
declaration	413	10.15		signal assignment statement	424	10.27
design file	393	10.4		signal declaration	414	10.17
entity declaration	394	10.7		special character	391	10.2
exit statement	430	10.33		subprogram body	416	10.20
generate statement	444	10.43		subprogram declaration	415	10.19
graphic character	391	10.1		type declaration	411	10.14
identifier	392	10.3		variable assignment statement	424	10.26
if statement	427	10.29		variable declaration	415	10.18
loop statement	429	10.31		wait statement	421	10.24

Appendix A contains more detailed definitions and technical reference material.

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