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10.14  Execution

Two successive statements may execute in either a concurrent or sequential fashion depending on where the statements appear.

statement_1; statement_2;

In sequential execution, statement_1 in this sequence is always evaluated before statement 2 . In concurrent execution, statement_1 and statement_2 are evaluated at the same time (as far as we are concerned--obviously on most computers exactly parallel execution is not possible). Concurrent execution is the most important difference between VHDL and a computer programming language. Suppose we have two signal assignment statements inside a process statement. In this case statement_1 and statement_2 are sequential assignment statements:

entity Sequential_1 is end; architecture Behave of Sequential_1 is
signal s1, s2 : INTEGER := 0; 
begin 
	process begin
		s1 <= 1;      -- sequential signal assignment 1
		s2 <= s1 + 1; -- sequential signal assignment 2
		wait on s1, s2 ; 
	end process; 
end;
      Time(fs) + Cycle            s1           s2 
----------------------  ------------ ------------ 
                  0+ 0:            0            0 
                  0+ 1: *          1 *          1 
                  0+ 2: *          1 *          2 
                  0+ 3: *          1 *          2

If the two statements are outside a process statement they are concurrent assignment statements, as in the following example:

entity Concurrent_1 is end; architecture Behave of Concurrent_1 is
signal s1, s2 : INTEGER := 0; begin 
	L1 : s1 <= 1;      -- concurrent signal assignment 1
	L2 : s2 <= s1 + 1; -- concurrent signal assignment 2
end;
      Time(fs) + Cycle            s1           s2 
----------------------  ------------ ------------ 
                  0+ 0:            0            0 
                  0+ 1: *          1 *          1 
                  0+ 2:            1 *          2

The two concurrent signal assignment statements in the previous example are equivalent to the two processes, labeled as P1 and P2 , in the following model.

entity Concurrent_2 is end; architecture Behave of Concurrent_2 is
signal s1, s2 : INTEGER := 0; begin 
	P1 : process begin s1 <= 1;      wait on s2 ; end process;
	P2 : process begin s2 <= s1 + 1; wait on s1 ; end process;
end; 
      Time(fs) + Cycle            s1           s2 
----------------------  ------------ ------------ 
                  0+ 0:            0            0 
                  0+ 1: *          1 *          1 
                  0+ 2: *          1 *          2 
                  0+ 3: *          1            2

Notice that the results are the same (though the trace files are slightly different) for the architectures Sequential_1, Concurrent_1, and Concurrent_2. Updates to signals occur at the end of the simulation cycle, so the values used will always be the old values. So far things seem fairly simple: We have sequential execution or concurrent execution. However, variables are updated immediately, so the variable values that are used are always the new values. The examples in Table 10.17 illustrate this very important difference.

TABLE 10.17    Variables and signals in VHDL.
Variables		Signals
entity Execute_1 is end; architecture Behave of Execute_1 is begin process variable v1 : INTEGER := 1; variable v2 : INTEGER := 2; begin v1 := v2; -- before: v1 = 1, v2 = 2 v2 := v1; -- after:  v1 = 2, v2 = 2 wait; end process; end;		entity Execute_2 is end; architecture Behave of Execute_2 is signal s1 : INTEGER := 1; signal s2 : INTEGER := 2; begin process begin s1 <= s2; -- before: s1 = 1, s2 = 2 s2 <= s1; -- after:  s1 = 2, s2 = 1 wait; end process; end;

The various concurrent and sequential statements in VHDL are summarized in Table 10.18.

TABLE 10.18    Concurrent and sequential statements in VHDL.
Concurrent [VHDL LRM9]		Sequential [VHDL LRM8]
block process concurrent_procedure_call concurrent_assertion concurrent_signal_assignment component_instantiation generate		wait assertion signal_assignment variable_assignment procedure_call if	case loop next exit return null

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