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Portions from Application-Specific Integrated Circuits Copyright 1997 by Addison Wesley Longman, Inc.

1.7 Problems

1.1 (Break-even volumes, 60 min.) You need a spreadsheet program (such as Microsoft Excel) for this problem.

1.2 (Design productivity, 10 min.) Given the figures for the SPARCstation 1 ASICs described in Section 1.3 what was the productivity measured in transistors/day? and measured in gates/day? Compare your answers with the figures for productivity in Section 1.4.3 and explain any differences. How accurate do you think productivity estimates are?

1.3 (ASIC package size, 30 min.) Assuming, for this problem, a gate density of 1.0 gate/mil 2 (see Section 15.4, “Estimating ASIC Size,” for a detailed explanation of this figure), the maximum number of gates you can put in a package is determined by the maximum die size for each of the packages shown in Table 1.4. The maximum die size is determined by the package cavity size; these are package-limited ASICs. Calculate the maximum number of I/O pads that can be placed on a die for each package if the pad spacing is: (i) 5 mil, and (ii) 10 mil. Compare your answers with the maximum numbers of pins (or leads) on each package and comment. Now calculate the minimum number of gates that you can put in each package determined by the minimum die size.

TABLE 1.4 Die size limits for ASIC packages.

Package 1

Number of pins or leads

Maximum die size 2 (mil 2 )

Minimum die size 3 (mil 2 )

PLCC

44

 

320 ¥ 320

94 ¥ 94

PLCC

68

 

420 ¥ 420

154 ¥ 154

PLCC

84

 

395 ¥ 395

171 ¥ 171

PQFP

100

 

338 ¥ 338

124 ¥ 124

PQFP

144

 

350 ¥ 350

266 ¥ 266

PQFP

160

 

429 ¥ 429

248 ¥ 248

PQFP

208

 

501 ¥ 501

427 ¥ 427

CPGA

68

 

480 ¥ 480

200 ¥ 200

CPGA

84

 

370 ¥ 370

200 ¥ 200

CPGA

120

 

480 ¥ 480

175 ¥ 175

CPGA

144

 

470 ¥ 470

250 ¥ 250

CPGA

223

 

590 ¥ 590

290 ¥ 290

CPGA

299

 

590 ¥ 590

470 ¥ 470

PPGA

64

 

230 ¥ 230

120 ¥ 120

PPGA

84

 

380 ¥ 380

150 ¥ 150

PPGA

100

 

395 ¥ 395

150 ¥ 150

PPGA

120

 

395 ¥ 395

190 ¥ 190

PPGA

144

 

660 ¥ 655

230 ¥ 230

PPGA

180

 

540 ¥ 540

330 ¥ 330

PPGA

208

 

500 ¥ 500

395 ¥ 395

1.4 (ASIC vendor costs, 30 min.) There is a well-known saying in the ASIC business: “We lose money on every part—but we make it up in volume.” This has a serious side. Suppose Sumo Silicon currently has two customers: Mr. Big, who currently buys 10,000 parts per week, and Ms. Smart, who currently buys 4800 parts per week. A new customer, Ms. Teeny (who is growing fast), wants to buy 1200 parts per week. Sumo’s costs are

wafer cost = $500 + ($250,000/ W ),

 

where W is the number of wafer starts per week. Assume each wafer carries 200 chips (parts), all parts are identical, and the yield is

yield = 70 + 0.2 ¥ ( W – 80) %

(1.3)

Currently Sumo has a profit margin of 35 percent. Sumo is currently running at 100 wafer starts per week for Mr. Big and Ms. Smart. Sumo thinks they can get 50 cents more out of Mr. Big for his chips, but Ms. Smart won’t pay any more. We can calculate how much Sumo can afford to lose per chip if they want Ms. Teeny’s business really badly.

1.5 (Silicon, 20 min.) How much does a 6-inch silicon wafer weigh? a 12-inch wafer? How much does a carrier (called a boat) that holds twenty 12-inch wafers weigh? What implications does this have for manufacturing?

1.6 (Simulation time, 30 min.) “. . . The system-level simulation used approximately 4000 lines of SPARC assembly language . . . each simulation clock was simulated in three real time seconds” (Sun Technology article).

The article continues: “the entire system was simulated, running actual code, including several milliseconds of SunOS execution. Four days after power-up, SPARCstation 1 booted SunOS and announced: 'hello world' .”

The number of clock cycles you need to simulate to boot a system is somewhere between your answers to parts d and e.

1.7 (Price per gate, 5 min.) Given the assumptions of Section 1.4.4 on the price per gate of different ASIC technologies, what has to change for the price per gate for an FPGA to be less than that for an MGA or CBIC—if all three use the same process?

1.8 (Pentiums, 20 min.) Read the online tour of the Pentium Pro at http://www.intel.com (adapted from a paper presented at the 1995 International Solid-State Circuits Conference). This is not an ASIC design; notice the section on full-custom circuit design. Notice also the comments on the use of 'assert' statements in the HDL code that described the circuits. Find out the approximate cost of the Intel Pentium (3.3 million transistors) and Pentium Pro (5.5 million transistors) microprocessors.

1.9 (Inverse embedded arrays, 10 min.) A relatively new cousin of the embedded gate array, the inverse-embedded gate array , is a cell-based ASIC that contains an embedded gate-array megacell. List the features as well as the advantages and disadvantages of this type of ASIC in the same way as for the other members of the ASIC family in Section 1.1.

1.10 (0.5-gate design, 60 min.) It is a good idea to complete a 0.5-gate ASIC design (an inverter connected between an input pad and an output pad) in the first week (day) of class. Capture the commands in a report that shows all the steps taken to create your chip starting from an empty directory— halfgate .

1.11 (Filenames, 30 min.) Start a list of filename extensions used in ASIC design. Table 1.5 shows an example. Expand this list as you use more tools.

TABLE 1.5 CAD tool filename extensions.

Extension

Description

From

To

.ini

Viewlogic startup file, library
search paths, etc.

Viewlogic/Viewdraw

Internal tools use

other Viewlogic tools

.wir

Schematic file

 


1. PLCC = plastic leaded chip carrier, PQFP = plastic quad flat pack, CPGA = ceramic pin-grid array, PPGA = plastic pin-grid array.

2. Maximum die size is not standard and varies between manufacturers.

3. Minimum die size is an estimate based on bond length restrictions.


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