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It is possible to test ICs in dual-in-line packages (DIPs ) with 0.1 inch (2.5 mm) lead spacing on low-density boards using a bed-of-nails tester with probes that contact test points underneath the board. Mechanical testing becomes difficult with board trace widths and separations below 0.1 mm or 100 mm, package-pin separations of 0.3 mm or less, packages with 200 or more pins, surface-mount packages on both sides of the board, and multilayer boards [ Scheiber, 1995].
In 1985 a group of European manufacturers formed the Joint European Test Action Group ( JETAG ) to study board testing. With the addition of North American companies, JETAG became the Joint Test Action Group ( JTAG ) in 1986. The JTAG 2.0 test standard formed the basis of the IEEE Standard 1149.1 Test Port and Boundary-Scan Architecture [ IEEE 1149.1b, 1994], approved in February 1990 and also approved as a standard by the American National Standards Institute (ANSI) in August 1990 [ Bleeker, v. d. Eijnden, and de Jong, 1993; Maunder and Tulloss, 1990; Parker, 1992]. The IEEE standard is still often referred to as JTAG, although there are important differences between the last JTAG specification (version 2.0) and the IEEE 1149.1 standard.
Boundary-scan test ( BST ) is a method for testing boards using a four-wire interface (five wires with an optional master reset signal). A good analogy would be the RS-232 interface for PCs. The BST standard interface was designed to test boards, but it is also useful to test ASICs. The BST interface provides a standard means of communicating with test circuits on-board an ASIC. We do need to include extra circuits on an ASIC in order to use BST. This is an example of increasing the cost and complexity (as well as potentially reducing the performance) of an ASIC to reduce the cost of testing the ASIC and the system.
Figure 14.1 (a) illustrates failures that may occur on a PCB due to shorts or opens in the copper traces on the board. Less frequently, failures in the ASIC package may also arise from shorts and opens in the wire bonds between the die and the package frame ( Figure 14.1 b). Failures in an ASIC package that occur during ASIC fabrication are caught by the ASIC production test, but stress during automated handling and board assembly may cause package failures. Figure 14.1 (c) shows how a group of ASICs are linked together in boundary-scan testing. To detect the failures shown in Figure 14.1 (a) or (b) manufacturers use boundary scan to test every connection between ASICs on a board. During boundary scan, test data is loaded into each ASIC and then driven onto the board traces. Each ASIC monitors its inputs, captures the data received, and then shifts the captured data out. Any defects in the board or ASIC connections will show up as a discrepancy between expected and actual measured continuity data.
In order to include BST on an ASIC, we add a special logic cell to each ASIC I/O pad. These cells are joined together to form a chain and create a boundary-scan shift register that extends around each ASIC. The input to a boundary-scan shift register is the test-data input ( TDI ). The output of a boundary-scan shift register is the test-data output ( TDO ). These boundary-scan shift registers are then linked in a serial fashion with the boundary-scan shift registers on other ASICs to form one long boundary-scan shift register. The boundary-scan shift register in each ASIC is one of several test-data registers ( TDR ) that may be included in each ASIC. All the TDRs in an ASIC are connected directly between the TDI and TDO ports. A special register that decodes instructions provides a way to select a particular TDR and control operation of the boundary-scan test process.
Controlling all of the operations involved in selecting registers, loading data, performing a test, and shifting out results are the test clock ( TCK ) and test-mode select ( TMS ). The boundary-scan standard specifies a four-wire test interface using the four signals: TDI, TDO, TCK, and TMS. These four dedicated signals, the test-access port ( TAP ), are connected to the TAP controller inside each ASIC. The TAP controller is a state machine clocked on the rising edge of TCK, and with state transitions controlled by the TMS signal. The test-reset input signal ( TRST* , nTRST , or TRST —always an active-low signal) is an optional (fifth) dedicated interface pin to reset the TAP controller.
Normally the boundary-scan shift-register cells at each ASIC I/O pad are transparent, allowing signals to pass between the I/O pad and the core logic. When an ASIC is put into boundary-scan test mode, we first tell the TAP controller which TDR to select. The TAP controller then tells each boundary-scan shift register in the appropriate TDR either to capture input data, to shift data to the neighboring cell, or to output data.
There are many acronyms in the IEEE 1149.1 standard (referred to as “ dot one ”); Table 14.3 provides a list of the most common terms.
Figure 14.2 shows a data-register cell ( DR cell ) that may be used to implement any of the TDRs. The most common DR cell is a boundary-scan cell ( BS cell , or BSC ), or boundary-register cell (this last name is not abbreviated to BR cell, since this term is reserved for another type of cell) [ IEEE 1149.1b-1994, p. 10-18, Fig. 10-16].
A BSC contains two sequential elements. The capture flip-flop or capture register is part of a shift register formed by series connection of BSCs. The update flip-flop , or update latch , is normally drawn as an edge-triggered D flip-flop, though it may be a transparent latch. The inputs to a BSC are: scan in ( serial in or SI ); data in ( parallel in or PI ); and a control signal, mode (also called test / normal ). The BSC outputs are: scan out ( serial out or SO ); data out ( parallel out or PO ). The BSC in Figure 14.2 is reversible and can be used for both chip inputs and outputs. Thus data_in may be connected to a pad and data_out to the core logic or vice versa.
The IEEE 1149.1 standard shows the sequential logic in a BSC controlled by the gated clocks: clockDR (whose positive edge occurs at the positive edge of TCK) and updateDR (whose positive edge occurs at the negative edge of TCK). The IEEE 1149.1 schematics illustrate the standard but do not define how circuits should be implemented. The function of the circuit in Figure 14.2 (and its model) follows the IEEE 1149.1 standard and many other published schematics, but this is not necessarily the best, or even a safe, implementation. For example, as drawn here, signals clockDR and updateDR are gated clocks—normally to be avoided if possible. The update sequential element is shown as an edge-triggered D flip-flop but may be implemented using a latch.
Figure 14.3 [ IEEE 1149.1b-1994, Chapter 9] shows a bypass-register cell ( BR cell ). The BR inputs and outputs, scan in (serial in, SI) and scan out (serial out, SO), have the same names as the DR cell ports, but DR cells and BR cells are not directly connected.
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clockDR,shiftDR,scan_in : BIT; scan_out : out BIT ); architecture behave of BR_cell is signal t1 : BIT; begin t1 <= shiftDR and scan_in; |
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Figure 14.4 shows an instruction-register cell ( IR cell ) [ IEEE 1149.1b-1994, Chapter 6]. The IR cell inputs are: scan_in , data_in ; as well as clock, shift, and update signals (with names and functions similar to those of the corresponding signals in the BSC). The reset signals are nTRST and reset_bar (active-low signals often use an asterisk, reset* for example, but this is not a legal VHDL name). The two LSBs of data_in must permanently be set to '01' (this helps in checking the integrity of the scan chain during testing). The remaining data_in bits are status bits under the control of the designer. The update sequential element (sometimes called the shadow register ) in each IR cell may be set or reset (depending on reset_value ). The IR cell outputs are: data_out (the instruction bit passed to the instruction decoder) and scan_out (the data passed to the next IR cell in the IR).
Figure 14.5 shows a boundary-scan register ( BSR ), which consists of a series connection, or chain, of BSCs. The BSR surrounds the ASIC core logic and is connected to the I/O pad cells. The BSR monitors (and optionally controls) the inputs and outputs of an ASIC. The direction of information flow is shown by an arrow on each of the BSCs in Figure 14.5 . The control signal, mode , is decoded from the IR. Signal mode is drawn as common to all cells for the BSR in Figure 14.5 , but that is not always the case.
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generic (width : INTEGER := 3); port (shiftDR, clockDR, updateDR, mode, scan_in : BIT; data_in : BIT_VECTOR(width-1 downto 0); data_out : out BIT_VECTOR(width-1 downto 0)); architecture structure of BSR is mode, data_in, shiftDR, scan_in, clockDR, updateDR : BIT; data_out, scan_out : out BIT); for all : DR_cell use entity WORK.DR_cell(behave); signal int_scan : BIT_VECTOR (data_in'RANGE); BSR : for i in data_in'LOW to data_in'HIGH generate BSR_LSB : DR_cell port map (mode, data_in(i), shiftDR, int_scan(i), clockDR, updateDR, data_out(i), scan_out); MIDDLE : if ((i > 0) and (i < data_in'HIGH)) generate BSR_i : DR_cell port map (mode, data_in(i), shiftDR, int_scan(i), clockDR, updateDR, data_out(i), int_scan(i-1)); LFET : if (i = data_in'HIGH) generate BSR_MSB : DR_cell port map (mode, data_in(i), shiftDR, |
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FIGURE 14.5 A BSR (boundary-scan register). An example of the component data-register (DR) cells (used as boundary-scan cells) is shown in Figure 14.2 . |
Figure 14.6 shows an instruction register ( IR ), which consists of at least two IR cells connected in series. The IEEE 1149.1 standard specifies that the IR cell is reset to '00...01' (the optional IDCODE instruction). If there is no IDCODE TDR, then the IDCODE instruction defaults to the BYPASS instruction.
Table 14.4 shows an instruction decoder . This model is capable of decoding the following minimum set of boundary-scan instructions:
The IEEE 1149.1 standard predefines additional optional instructions and also defines the implementation of custom instructions that may use additional TDRs.
Figure 14.7 shows the TAP controller finite-state machine. The 16-state diagram contains some symmetry: states with suffix '_DR' operate on the data registers and those with suffix '_IR' apply to the instruction register. All transitions between states are determined by the TMS (test mode select) signal and occur at the rising edge of TCK , the boundary-scan clock. An optional active-low reset signal, nTRST or TRST* , resets the state machine to the initial state, Reset . If the dedicated nTRST is not used, there must be a power-on reset signal (POR)—not an existing system reset signal.
The outputs of the TAP controller are not shown in Figure 14.7 , but are derived from each TAP controller state. The TAP controller operates rather like a four-button digital watch that cycles through several states (alarm, stopwatch, 12 hr / 24 hr, countdown timer, and so on) as you press the buttons. Only the shaded states in Figure 14.7 affect the ASIC core logic; the other states are intermediate steps. The pause states let the controller jog in place while the tester reloads its memory with a new set of test vectors, for example.
Table 14.5 shows the output control signals generated by the TAP state machine. I have taken the unusual step of writing separate entities for the state machine and its outputs. Normally this is bad practice because it makes it difficult for synthesis tools to extract and optimize the logic, for example. This separation of functions reflects the fact that the operation of the TAP controller state machine is precisely defined by the IEEE 1149.1 standard—independent of the implementation of the register cells and number of instructions supported. The model in Table 14.5 contains the following combinational, registered, and gated output signals and will change with different implementations:
The signals reset_bar , enableTDO , shiftIR , and shiftDR are registered or clocked by TCK (on the positive edge of TCK ). We say these signals are clean (as opposed to being dirty gated clocks).
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TABLE 14.5 The TAP (test-access port) control. 1 |
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use work.TAP. all ; entity TAP_sm_output is port (TCK : in BIT; S : in TAP_STATE; reset_bar, selectIR, enableTDO, shiftIR, clockIR, updateIR, shiftDR, clockDR, updateDR : out BIT); architecture behave_1 of TAP_sm_output is begin -- registered outputs process (TCK) begin if ( (TCK = '0') and TCK'EVENT ) then if S = Reset then reset_bar <= '0'; else reset_bar <= '1'; end if ; if S = Shift_IR or S = Shift_DR then enableTDO <= '1'; else enableTDO <= '0'; end if ; if S = Shift_IR then ShiftIR <= '1'; else shiftIR <= '0'; end if ; if S = Shift_DR then ShiftDR <= '1'; else shiftDR <= '0'; end if ; process (TCK) begin -- dirty outputs gated with not(TCK) if (TCK = '0' and (S = Capture_IR or S = Shift_IR)) then clockIR <= '0'; else clockIR <= '1'; end if ; if (TCK = '0' and (S = Capture_DR or S = Shift_DR)) then clockDR <= '0'; else clockDR <= '1'; end if ; if TCK = '0' and S=Update_IR then updateIR <= '1'; else updateIR <= '0'; end if ; if TCK = '0' and S=Update_DR then updateDR <= '1'; else updateDR <= '0'; end if ; selectIR <= '1' when (S = Reset or S = Run_Idle or S = Capture_IR or S = Shift_IR or S = Exit1_IR or S = Pause_IR or S = Exit2_IR or S = Update_IR) else '0'; |
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Figure 14.8 shows a boundary-scan controller. It contains the following four parts:
The BSR (and other optional TDRs) are connected to the ASIC core logic outside the BST controller.
Figure 14.9 shows an example of a simple ASIC (our comparator/MUX example) containing boundary scan. The following two packages define the TAP states and the components (these are not essential to understanding what follows, but are included so that the code presented here forms a complete BST model):
type TAP_STATE is (reset, run_idle, select_DR, capture_DR,
shift_DR, exit1_DR, pause_DR, exit2_DR, update_DR, select_IR,
capture_IR, shift_IR, exit1_IR, pause_IR, exit2_IR, update_IR);
use work.TAP. all ; library IEEE; use IEEE.std_logic_1164. all ;
mode, data_in, shiftDR, scan_in, clockDR, updateDR: BIT;
data_out, scan_out : out BIT );
shiftIR, data_in, scan_in, clockIR, updateIR, reset_bar,
nTRST, reset_value : BIT; data_out, scan_out : out BIT);
clockDR,shiftDR,scan_in : BIT; scan_out: out BIT );
generic (width : INTEGER := 5); port (
shiftDR, clockDR, updateDR, mode, scan_in : BIT;
data_in : BIT_VECTOR(width-1 downto 0);
data_out : out BIT_VECTOR(width-1 downto 0));
component IR generic (width : INTEGER := 4); port (
shiftIR, clockIR, updateIR, reset_bar, nTRST,
scan_in : BIT; scan_out : out BIT;
data_in : BIT_VECTOR (width-1 downto 0) ;
data_out : out BIT_VECTOR (width-1 downto 0) );
component IR_decoder generic (width : INTEGER := 4); port (
shiftDR, clockDR, updateDR : BIT;
IR_PO : BIT_VECTOR (width-1 downto 0);
test_mode, selectBR, shiftBR, clockBR, shiftBSR, clockBSR,
component TAP_sm_states port (
TMS, TCK, nTRST : in BIT; S : out TAP_STATE); end component ;
component TAP_sm_output port (
TCK: BIT; S : TAP_STATE; reset_bar, selectIR,
enableTDO, shiftIR, clockIR, updateIR, shiftDR, clockDR,
component Control generic (width : INTEGER := 2); port (
TMS, TCK, TDI, nTRST : BIT; TDO : out STD_LOGIC;
BSR_SO : BIT; BSR_PO : BIT_VECTOR (width-1 downto 0);
shiftBSR, clockBSR, updateBSR, test_mode : out BIT);
TMS, TCK, TDI : BIT; TDO : out STD_LOGIC;
a_PAD, b_PAD : BIT_VECTOR (2 downto 0);
z_PAD : out BIT_VECTOR (2 downto 0));
The following testbench, Test_BST , performs these functions:
library IEEE; use IEEE.std_logic_1164. all ;
library STD; use STD.TEXTIO. all ;
architecture behave of Test_BST is
component BST_ASIC port (TMS, TCK, TDI, nTRST: BIT;
TDO : out STD_LOGIC; a_PAD, b_PAD : BIT_VECTOR (2 downto 0);
z_PAD : out BIT_VECTOR (2 downto 0));
for all : BST_ASIC use entity work.BST_ASIC(behave);
signal TMS, TCK, TDI, nTRST : BIT; signal TDO : STD_LOGIC;
signal TDI_TMS : BIT_VECTOR (1 downto 0);
signal a_PAD, b_PAD, z_PAD : BIT_VECTOR (2 downto 0);
TDI <= TDI_TMS(1) ; TMS <= TDI_TMS(0) ;
(TMS, TCK, TDI, nTRST, TDO, a_PAD, b_PAD, z_PAD);
nTRST <= '1', '0' after 10 ns, '1' after 20 ns; wait ;
a_PAD <= ('0', '1', '0'); b_PAD <= ('0', '1', '1'); wait ;
TCK_DRIVE : process begin -- rising edge at 100 ns
TCK <= '0' after 50 ns, '1' after 100 ns; wait for 100 ns;
if (now > 3000 ns) then wait ; end if ;
BST_DRIVE : process begin TDI_TMS <=
('0', '1') after 0 ns, -- Reset
('0', '0') after 101 ns, -- Run_Idle
('0', '1') after 201 ns, -- Select_DR
('0', '1') after 301 ns, -- Select_IR
('0', '0') after 401 ns, -- Capture_IR
('0', '0') after 501 ns, -- Shift_IR
('1', '0') after 601 ns, -- Shift_IR
('0', '1') after 701 ns, -- Exit1_IR
('0', '1') after 801 ns, -- Update_IR, 01 = SAMPLE/PRELOAD
('0', '1') after 901 ns, -- Select_DR
('0', '0') after 1001 ns, -- Capture_DR
('0', '0') after 1101 ns, -- Shift_DR
-- shift 111111101 into BSR, TDI(time) = 101111111 starting now
('1', '0') after 1201 ns, -- Shift_DR
('0', '0') after 1301 ns, -- Shift_DR
('1', '0') after 1401 ns, -- Shift_DR -- shift 4 more 1's
('1', '0') after 1901 ns, -- Shift_DR -- in-between
('1', '1') after 2001 ns, -- Exit1_DR
('0', '1') after 2101 ns, -- Update_DR
('0', '1') after 2201 ns, -- Select_DR
('0', '1') after 2301 ns, -- Select_IR
('0', '0') after 2401 ns, -- Capture_IR
('0', '0') after 2501 ns, -- Shift_IR
('0', '0') after 2601 ns, -- Shift_IR
('0', '1') after 2701 ns, -- Exit1_IR
('0', '1') after 2801 ns, -- Update_IR, 00=EXTEST
('0', '0') after 2901 ns; -- Run_Idle
process (TDO, a_pad, b_pad, z_pad) variable L : LINE; begin
write (L, now, RIGHT, 10); write (L, STRING'(" TDO="));
if TDO = 'Z' then write (L, STRING'("Z")) ;
else write (L, TO_BIT(TDO)); end if ;
write (L, STRING'(" PADS=")); write (L, a_pad & b_pad & z_pad);
Here is the output from this testbench:
# 1250 ns TDO=0 PADS=010011010
# 1350 ns TDO=1 PADS=010011010
# 1450 ns TDO=0 PADS=010011010
# 1550 ns TDO=1 PADS=010011010
# 1750 ns TDO=0 PADS=010011010
# 1950 ns TDO=1 PADS=010011010
# 2050 ns TDO=0 PADS=010011010
# 2150 ns TDO=Z PADS=010011010
# 2650 ns TDO=1 PADS=010011010
# 2750 ns TDO=0 PADS=010011010
# 2850 ns TDO=Z PADS=010011010
# 2950 ns TDO=Z PADS=010011101
This trace shows the following activities:
Figure 14.10 shows a signal trace from the MTI simulator for the last four negative edges of TCK . Notice that we shifted in the test pattern on TDI in the order '101111111' . The output z_pad (3 bits wide) is last in the BSR (nearest TDO ) and thus is driven with the first 3 bits of this pattern, '101' . Forcing '101' onto the ASIC output pins would allow us to check that this pattern is correctly received at inputs of other connected ASICs through the bonding wires and board traces. In a later test cycle we can force '010' onto z_pad to check that both logic levels can be transmitted and received. We may also capture other signals (which are similarly being forced onto the outputs of neighboring ASICs) at the inputs.
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FIGURE 14.10 Results from the MTI simulator for the boundary-scan testbench. |
The boundary-scan description language ( BSDL ) is an extension of IEEE 1149.1 but without any overlap. BSDL uses a subset of VHDL. The BSDL for an ASIC is part of an imaginary data sheet; it is not intended for simulation and does not include models for any boundary-scan components. BSDL is a standard way to describe the features and behavior of an ASIC that includes IEEE 1149.1 boundary scan and a standard way to pass information to test-generation software. Using BSDL, test software can also check that the BST features are correct. As an example, test software can use the BSDL to check that the ASIC uses the correct boundary-scan cells for the instructions that claim to be supported. BSDL cannot prove that an implementation works, however.
The following example BSDL description corresponds to our halfgate ASIC example with BST (this code was generated automatically by the Compass tools):
generic (PHYSICAL_PIN_MAP : STRING := "DUMMY_PACKAGE");
pad_a: in BIT_VECTOR (0 to 0);
pad_z: buffer BIT_VECTOR (0 to 0);
attribute PIN_MAP of asic_p : entity is PHYSICAL_PIN_MAP;
-- CUSTOMIZE package pin mapping.
constant DUMMY_PACKAGE : PIN_MAP_STRING :=
attribute TAP_SCAN_IN of TDI : signal is TRUE;
attribute TAP_SCAN_MODE of TMS : signal is TRUE;
attribute TAP_SCAN_OUT of TDO : signal is TRUE;
attribute TAP_SCAN_RESET of TRST : signal is TRUE;
-- CUSTOMIZE TCK max freq and safe stop state.
attribute TAP_SCAN_CLOCK of TCK : signal is (20.0e6, BOTH);
attribute INSTRUCTION_LENGTH of asic_p : entity is 3;
attribute INSTRUCTION_OPCODE of asic_p : entity is
attribute INSTRUCTION_CAPTURE of asic_p : entity is "001";
-- attribute INSTRUCTION_DISABLE of asic_p : entity is " "
-- attribute INSTRUCTION_GUARD of asic_p : entity is " "
-- attribute INSTRUCTION_PRIVATE of asic_p : entity is " "
attribute IDCODE_REGISTER of asic_p : entity is
"0000000000000000" & -- 16-bit part number
"00000101011" & -- 11-bit manufacturer
-- attribute USERCODE_REGISTER of asic_p : entity is " "
attribute REGISTER_ACCESS of asic_p : entity is
attribute BOUNDARY_CELLS of asic_p : entity is
attribute BOUNDARY_LENGTH of asic_p : entity is 2;
attribute BOUNDARY_REGISTER of asic_p : entity is
-- num cell port function safe [ccell disval rslt]
" 1 ( BC_2, pad_a(0), input, X)," &
" 0 ( BC_1, pad_z(0), output2, X)";
-- " 98 ( BC_1, OE, input, X), " &
