6.9 Summary

Among the options available in I/O cells are: different drive strengths, TTL-compatibility, registered or direct inputs, registered or direct outputs, pull-up resistors, over-voltage protection, slew-rate control, and boundary-scan. Table 6.4 shows a list of features. Interfacing an ASIC with a system starts at the outputs where you check the voltage levels first, then the current levels. Table 6.5 is a look-up table for Tables 6.6 and 6.7 , which show the I/O resources present in each type of programmable ASIC (using the abbreviations of Table 6.4 ).

TABLE 6.4 I/O options for programmable ASICs.
Code ¹	I/O Option	Function
IT/C	TTL/CMOS input	Programmable input buffer threshold
OT/C	TTL/CMOS output	Complementary or totem-pole output
nSNK	Sink capability	Maximum current sink ability (e.g., 12SNK is I ₀ = 12 mA sink)
nSRC	Source capability	Maximum current source ability (e.g., 12SRC is I ₀ = –12 mA source)
5/3	5V/3V	Separate I/O and core voltage supplies
OD	Open drain/collector	Programmable open-drain at the output buffer
TS	Three-state	Output buffer with three-state control
SR	Slew-rate control	Fast or slew-rate limited output buffer to reduce ground bounce
PD	Pull-down	Programmable pull-down device or resistor at the I/O pad
PU	Pull-up	Programmable pull-up device or resistor at the I/O pad
EP	Enable polarity	Driver control can be positive (three-state) or negative (enable).
RI	Registered input	Inputs may be registered in I/O cell.
RO	Registered output	Outputs may be registered in I/O cell.
RIO	Registered I/O	Both inputs and outputs may be registered in I/O cell.
ID	Input delay	Input delay to eliminate input hold time
JTAG	JTAG	Boundary-scan test
SCH	Schmitt trigger	Schmitt trigger or input hysteresis
HOT	Hot insertion	Inputs protected from hot insertion
PCI	PCI compliant	Output buffer characteristics comply with PCI specifications.

Important points that we covered in this chapter are the following:

Outputs can typically source or sink 5–10 mA continuously into a DC load, and 50–200 mA transiently into an AC load.
Input buffers can be CMOS (threshold at 0.5 V _DD ) or TTL (1.4 V).
Input buffers normally have a small hysteresis (100–200 mV).
CMOS inputs must never be left floating.
Clamp diodes to GND and VDD are present on every pin.
Inputs and outputs can be registered or direct.
I/O registers can be in the I/O cell or in the core.
Metastability is a problem when working with asynchronous inputs.

1. These codes are used in Tables 6.6 and 6.7 .

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